Highly Reliable Arithmetic Multipliers for Future Technologies
نویسنده
چکیده
Future technologies, below 90nm, will present transistors so small that they will be heavily influenced by electromagnetic noise and SEU induced errors. This way, together with process variability, design as known today is likely to change. Since several soft errors may occur in a small period of time, the traditional hypothesis that the behavior of a gate is fixed is no longer valid and a different design approach must be taken. The use of inherently robust operators as an alternative to conventional digital arithmetic operators is proposed in this study. The behavior of the proposed operators is analyzed through the simulation of single and multiple random faults injection, and the proposed circuits are robust to severe noise and single event upsets, standing multiple simultaneous faults. The number of tolerated upsets varies according to the number of extra bits appended to the operands, and is limited only by the area restriction.
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